1. Field of the Invention
The present invention relates to an electronic exchange with a hot standby memory copy system including main storage devices that are duplexed.
The hot standby system including the duplexed main storage or main memory devices (hereinafter called MMs) is a system conventionally used in an electronic exchange. In the hot standby system, a writing operation is carried out by a current central processing unit (hereinafter called the CPU) using both MMs, while a reading operation is performed with one of the MMs. A feature of this system is that the contents of both MMs are guaranteed to be equal to each other. When an abnormality of the MM is detected (for example, detection of a parity error, a two-bit error, etc.,), the read MM is switched to the other MM to enable a current process to be continued, and accordingly, compared to a system used in a general computer where a portion after a check point is re-tried, the system can be started quicker.
In such a hot standby system, by using elements having high operation speeds, a machine cycle of the CPU may be shortened, but an access time to the MMs is still long, and thus a problem arises related to an imbalance between an operation speed of the CPU and the access time to the MMs.
To solve the above-mentioned imbalance, a cache memory is arranged between the CPU and the MM so that, if the cache memory contains address contents requested by the CPU, that is, if the cache memory hits the required contents, data is read from the cache memory but not from the MM, and if it does not hit (miss) the required contents, the contents of the cache memory that are least frequently used are updated or replaced.
There are two modes of use of the cache memory i.e., a write through mode and a copy back mode.
In the write through mode, whenever the CPU requests an update of the contents of the memory, the cache memory as well as the MM are updated. Since data is not saved from the MM to the cache memory, control is simple, but a drawback arises in that positive effects of the cache memory are demonstrated only during a reading operation.
In the copy back mode, whenever the CPU requests an update of the contents of the memory, only the contents of the cache memory are updated, and thus it is appropriate for a high-speed operation. But, a saving operation from the MM with respect to the cache memory is required, and a problem arises in that the control related to this operation is complicated.
In a system using the cache memory, a memory copy system is needed to make the best use of the high-speed of the cache memory.
2. Description of the Related Art
FIG. 16 is a block diagram for explaining a conventional hot standby system with duplexed CPUs and MMs but without a cache memory. In the figure, a CPU 160 and an MM 161 belong to a current system and a CPU 160' and an MM 161' belong to a standby system. In this system, there is no cache memory so that, even if the speed of the CPUs is increased, an access speed with respect to the MMs is still slow, and thus the problem arises in that a processing capacity of the system as a whole is not improved. Further, if high speed MMs are provided to improve the processing capacity of the whole system, the costs will be increased.
FIG. 17 is a block diagram showing an example of a conventional dual system using duplexed CPUs and MMs with cache memories. In the figure, a CPU 170, a cache memory 171, and an MM 172 belong to a current system, and a CPU 170', a cache memory 171', and an MM 172' belong to a standby system. According to this conventional example, the cache memories constitute part of the CPUs, and the current cache memory 171 is connected to the current MM 172 and standby MM 172', and similarly, the standby cache memory 171' is connected to the standby MM 172' and current MM 172.
To use the system of FIG. 17 in the copy back mode, the CPU carries out writing and reading operations to and from the cache memory so that the processing speed is improved. But, in response to a memory contents updating request from the CPU, the contents of only the cache memory are updated so that the cache memory may have data that does not exist in the MMs. Therefore, although the contents of the MMs 172 and 172' are always the same, the contents of the cache memory 171 may differ from that of the cache memory 171'. Therefore, if the current CPU is switched to the standby CPU due to a fault in the cache memory 171, data existing only in the current cache memory is lost, and thus the hot standby mode is not realized.
It is possible to apply the system shown in FIG. 17 to the write through mode. According to the write through mode, a writing operation is carried out simultaneously to both the MMs through the cache memory, so that the problem of the copy back mode wherein data exist only in the cache memory, will not occur.
The duplexed CPUs and MMs, however, are generally connected to separate power supply systems so that buffer gates, etc., are inserted in the cross connections between the cache memories and the MMs. Therefore, to write data from the CPU to both the MMs by passing through the cache memory, the necessary access time for the other system is longer than the necessary access time for the current system, due to delays in the buffer gates and cables, etc., of the cross connections.
For example, assume that the main storage comprises a memory having a cycle time of 180 ns and that a cycle time of 200 ns the main storage for the current system. But, with respect to the other system, the above-mentioned additional delays are added and, if the delays are 20 ns at the gates and 5 ns at the cables, the actual cycle time will be 225 ns. Namely, a loss due to the cross connections will be 10% or more.
The delay due to the cross connections may not always decrease a processing capacity of the CPU, but if it is assumed that it will affect half thereof, about 5% of the processing capacity is affected. It is very difficult to increase the processing capacity or speed of the CPU by 5%, and therefore, it is very important to prevent a decrease of the processing capacity caused by the cross connections.
FIG. 18 is a block diagram showing another example of the conventional duel system including duplexed CPUs and MMs employing cache memories. In the figure, a CPU 180, a cache memory 181, and an MM 182 belong to a current system, and a CPU 180', a cache memory 181', and an MM 182' belong to a standby system. In this prior art example, the cache memories are part of the MMs, respectively. The current CPU 180 is connected to the current and standby cache memories 181 and 181', and similarly, the standby CPU 180' is connected to the standby and current cache memories 181' and 181.
This example is used for the copy back mode and is a hot standby system, but since cross connections exist between the CPUs and the cache memories, the high speed of the cache memories is not properly utilized.
Namely, it is necessary to synchronize the hits and misses of both cache memories, but due to the length of a bus from the current CPU to the other cache memory and a delay time of a buffer memory at an input portion of the cache memory, an access time from the CPU to the current cache memory is delayed, and as a result, the cache access speed is lowered. Since the speeds of the CPUs and cache memories tend to be increased, the cross connection delay of the arrangement shown in the figure reaches 20% to 50% of the cache memory access time.